+------------------------------------------------------------------------- | | 6510 CPU ILLEGAL INSTRUCTION SET | +------------------------------------------------------------------------- | | Related topics: | | 6510 instruction set | 6510 instruction chart | | 65816 extended instruction set | 65816 instruction chart | | 6510/65816 Addressing modes | | Instructions set: | | ANC Accu AND with memory, copy accu-bit 7 to carry | ANE Instable! | ARR Accu AND with memory, ROR accu | ASR Accu AND with memory, LSR accu | | DCP DEC memory, CMP memory | | ISB INC memory, SBC memory | | JAM Locks up machine | | LAE Instable! | LAX LDA memory, TAX | LXA Instable! | | NOP No operation | | RLA ROL memory, AND accu, result into accu | RRA ROR memory, ADC accu, result into accu | | SAX Accu AND with X-Register, result into memory | SBC Subtract memory from accumulator with borrow | SBX X-Register AND with accu, SBC memory, result into X-Register | SHA Instable! | SHS Instable! | SHX Instable! | SHY Instable! | SLO ASL memory, ORA accu, result into accu | SRE LSR memory, EOR accu, result into accu | +------------------------------------------------------------------------- Back to Mainpage