.------------------------------------------------------. | MC680x0 Assembly Source to Power-PC Conversion Chart | `------------------------------------------------------' Written for the - Digital Candy CD - With the event of Amiga Technologies naming Motorola`s PowerPC Reduced instruction micro processor as the successor to the MC68000`s series in the beloved Amiga we present you some information regarding the PowerPC chip`s. This text is a PowerPC Instruction Reference. This text contains a lot of helpful descriptions for `porting' MC680x0 written assembly language source over to PowerPC assembly. An "automatic" source-code translator should be available for mid `96 on Digital Candy!. This will do 90% of the assembly translation process automatically for you hence making conversion much less painful! Please note that really the PowerPC RISC chips are nothing more than redesigned from ground up MC680x0 cpu`s. Nothing stupid like Intel`s efforts with 8086 and the like! - Thank god! :) A useful purpose of releasing this information is to make coders aware of the unsupported MC680x0 instructions that don`t exist on the PPC chips. This will allow MC680x0 coders to write future MC68000 code that doesn`t use them - this will help making translation of your MC68000 source much easier! For a full description of the PowerPC instruction set keep an eye out on Digital Candy BBS. Enjoy! .---------------------.---------------.-------------------------------------. | Description | Asm MC680x0 | PowerPC Description | `---------------------^---------------^-------------------------------------' Add BCD ABCD (000+) Not supported directly. Add ADD (000+) Use suitable add instruction. Add Address ADDA (000+) Use suitable add instruction. Add Immediate ADDI (000+) Use add immediate if immediate value is not greater than 16 bits. Use a register to create a tempory immediate value if a larger immediate value is needed. Add Quick ADDQ (000+) Use add immediate. Add with Extend ADDX (000+) Use suitable add instruction. Logical AND AND (000+) Use the and instruction. Logical AND ANDI (000+) Use and immediate instruction. with Immediate Arithmetic Shift Left ASL (000+) Use appropriate rotate or shift left instruction to simulate the operation. Arithmetic Shift Left ASR (000+) Use appropriate rotate or shift right instruction to simulate the operation Branch if Condition Bcc (000+) Use appropritae branch instruction is True (e.g. BNE.) taking into account speculative execution. (see doc`s) Test bit and change BCHG (000+) Not supported directly. Requires simulation using the reservation station technique to provide the atomic operation. (see doc`s) Test bit and clear BCLR (000+) Not supported directly. Requires simulation using the reservation station technique to provide the atomic operation. (see doc`s) Test bit field and BFCHG (020+) Not supported directly. Requires change simulation using the reservation station technique to provide the atomic operation. (see doc`s) Test bit field and BFCLR (020+) Not supported directly. Requires clear simulation using the reservation station technique to provide the atomic operation. (see doc`s) Extract signed bit BFEXTS (020+) Use an appropritate rotate or field shift instruction to simulate the operation. Extract unsigned bit BFEXTU (020+) Use an appropritate rotate or field shift left instruction to simulate the operation. Bit field find first 1 BFFFO (020+) Use an appropritate rotate or shift field left instruction(s) to simulate the operation. Count leading zeros can also be used as part of simulation. Insert Bit field BFINS (020+) Use an appropriate roatate or shift instructions(s). Test bit field & Set BFSET (020+) Not supported directly. Simulate using the reservation station technique to provide the atomic operation. Test bit field BFTST (020+) Not supported directly. Simulate using the reservation station technique to provide the atomic operation. Set Breakpoint BKPT (000+) Not supported directly. Use breakpoint registers in the cpu supervisor model to set breakpoints. Unconditional branch BRA (000+) Use Branch always instruction. Set Bit BSET (000+) Not supported directly. Simulation is required using reservation station technique to provide the atomic operation. Branch to subroutine BSR (000+) Use a suitable branch instruction that uses the link register. The choice will depend on how far your target address is. The link register contents may need saving in order to preserve the context of any previous branches. The system call instruction can also be used in some circumstances. Messy? Answers On a postcard to Motorola please. Hopefully the PowerPC assemblers will do this part automatically for coders. Test Bit BTST (000+) Not supported directly. Simulation is required using reservation station technique to provide the atomic operation. Call Module CALLM (020+) Not supported directly. Compare & Swap Operands CAS (000+) Not supported directly. Simulation is required using reservation station technique to provide the atomic operation. Compare & Swap Dual Ops CAS2 (020+) Not supported directly. Simulation is required using reservation station technique to provide the atomic operation. Check Reg Against Bound CHK (000+) Not supported directly. Simulation is required using reservation station technique to provide the atomic operation. Check Upr/lower Bound CHK2 (020+) Not supported directly. Simulation is required using reservation station technique to provide the atomic operation. Clear CLR (000+) Use R0 within an add or logical operation to write $00000000 into the target register. If the location is in external memory, use a store instruction with R0 instead. Compare CMP (000+) Not supported directly. Simulation is required using reservation station technique to provide the atomic operation. Compare Upr/Lower Bound CMP2 (020+) Not supported directly. Simulation is required using reservation station technique to provide the atomic operation. Compare Address CMPA (000+) Use a suitable compare instruction. Compare Immediate CMPI (000+) Use a suitable compare instruction. Cmp Memory with Memory CMPM (000+) Not supported directly. Simulation is required using reservation station technique to provide the atomic operation. Test,decrement,branch DBcc (000+) Use branch instruction that if Condition is true decrements the CTR register to simulate. Signed Divide DIVS (000+) Use the divide instruction but remember that PowerPC cpu`s instructions do not create remainder directly. Signed Divide DIVSL (020+) Use the divide instruction but remember that PowerPC cpu`s instructions do not create remainder directly. Unsigned Divide DIVU (000+) Use the divide instruction but remember that PowerPC cpu`s instructions do not create remainder directly. Unsigned Divide DIVUL (020+) Use the divide instruction but remember that PowerPC cpu`s instructions do not create remainder directly. Exclusive Logical OR EOR (000+) Use the XOR instruction. Exclusive OR Immediate EORI (000+) Use the XORI instruction. Exchange Registers EXG (000+) Not supported directly. Sign Extend EXT (000+) Use an extend instruction. Sign Extend EXTB (000+) Use the extend byte instruction Illgal Opcode Trap ILLEGAL (000+) Illegal opcode will be trapped out by PowerPC Cpu`s. Hence there is no defined illegal instruction. Any invalid instruction will do. Jump JMP (000+) Use a branch always instruction Load Effective Address LEA (000+) Use an add immediate instruction Link register to stack LINK (000+) Not supported directly. Logical Shift Left LSL (000+) Use appropriate rotate or shift left instruction to simulate the operation. Logical Shift Left LSR (000+) Use appropriate rotate or shift right instruction to simulate the operation Move Condition Code MOVE CCR (000+) Use a CCR instruction to move the contents of a condition field to another. Use a move to or move from condition register instruction. Move Address MOVEA (000+) Use an add or logical instruction to move the register contents to another register. A store instruction will be needed to mvoe the contents to memory. Move Status Register MOVE SR (000+) Use the move to and from MSR instructions. Move User Stack MOVE USP (000+) Use an add or logical instruction Pointer to move the register contents to another register. A store instruction will be needed to mvoe the contents to memory. Move Control Register MOVEC (020+) Use an appropritate move to and move from instruction e.g. move to special purpose register. Move Multiple registers MOVEM (000+) Use store multiple words to move registers to memory. Use the Load multiple words to restore them. Move peripheral data MOVEP (000+) Not supported directly. Move Quick MOVEQ (000+) Use an Add or logical immediate instruction to simulate. Move alternative MOVES (020+) Not supported directly. address space Signed Multiply MULS (000+) Use the Multiply High and low instructions to simulate the multiply instruction Unsigned Multiply MULU (000+) Use the Multiply High and low instructions to simulate the multiply instruction Negate BCD data NBCD (000+) Not supported directly. Negate NEG (000+) Not supported directly. Negate with extend NEGX (000+) Not supported directly. No-operation NOP (000+) Not supported directly. Simulate with logic operation that uses register 0 (r0) to do nothing. E.g. in PPC code; ORI 0,0,0 Logical Complement NOT (000+) Use NAND instruction Logical OR OR (000+) Use the OR instruction Logical OR Immediate ORI (000+) Use the OR Immediate instruction Pack BCD data PACK (020+) Not supported directly. Push Effective address PEA (000+) Not supported directly. Manipulate addresses directly. Reset Peripherals RESET (000+) Not supported directly. Rotate Bits Left ROL (000+) Use an appropriate rotate instruction Rotate Bits Right ROR (000+) Use an appropriate rotate instruction Rotate Bits Left with ROXL (000+) Use an appropriate rotate instruction Extend Rotate Bits Right with ROXL (000+) Use an appropriate rotate instruction Extend Return from Exception RTE (000+) Now called the Return-From-Interrupt in PPC terminology hence use, RTI. Return from Module RTM (020+) Not supported directly. Return and Restore RTR (020+) Not supported directly. Return from Subroutine RTS (000+) Use branch always instruction with the destination address in the link register. Subtract BCD SBCD (000+) Not supported directly. Set byte conditionally Scc (000+) Not supported directly. Stop cpu STOP (000+) Not supported directly. Subtract Memory SUB (000+) Use an appropriate subtract instruction Subtract Address SUBA (000+) Use an appropriate subtract instruction Subtract Immediate SUBI (000+) Use an appropriate subtract instruction Subtract Quick SUBQ (000+) Use an appropriate subtract instruction Subtract with Extend SUBX (000+) Use an appropriate subtract instruction Swap register words SWAP (000+) Not supported directly. Test operand and set TAS (000+) Not supported directly. Who care`s though? The Amiga never supported it anyway due to hardware contention. Trap TRAP (000+) Not supported directly. Conditional Trap TRAPcc(000+) Not supported directly. Trap on Overflow TRAPV (000+) Not supported directly. Test operand TST (000+) Not supported directly. Unlink from stack UNLK (000+) Not supported directly. Unpack BCD data UNPK (000+) Not supported directly. ----------------------------------------------------------------------------- End.